1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor structure, and more particularly, to a manufacturing method of a semiconductor structure for improving the quality of epitaxial layers in the semiconductor structure.
2. Description of the Prior Art
In order to increase the carrier mobility of semiconductor structure, it has been widely used to apply tensile stress or compressive stress to a gate channel. For instance, if a compressive stress were to be applied, it has been common in the conventional art to use selective epitaxial growth (SEG) technique to form epitaxial structure such as a silicon germanium (SiGe) epitaxial layer in a silicon substrate. As the lattice constant of the SiGe epitaxial layer is greater than the lattice constant of the silicon substrate thereby producing stress to the channel region of a PMOS transistor, the carrier mobility is increased in the channel region and speed of MOS transistor is improved accordingly. Conversely, a silicon carbide (SiC) epitaxial layer could be formed in silicon substrate to produce tensile stress for gate channel of an NMOS transistor.
In the procedure of forming the epitaxial layer, the growth condition of the epitaxial layer will be affected by impurities around the target area, such as a recess in the silicon substrate. The condition of defects, such as stacking faults, in the epitaxial layer will become worse, and the electrical properties of the MOS transistor may be influenced accordingly. In addition, if the impurities are unevenly distributed, the defect conditions of the epitaxial layers corresponding to different transistors will be different from one another more obviously, and the electrical characteristic uniformity of the transistors may become worse too.